The fabrication of various solid state devices requires the use of planar substrates, or semiconductor wafers, on which integrated circuits are fabricated. The final number, or yield, of functional integrated circuits on a wafer at the end of the IC fabrication process is of utmost importance to semiconductor manufacturers, and increasing the yield of circuits on the wafer is the main goal of semiconductor fabrication. After packaging, the circuits on the wafers are tested, wherein non-functional dies are marked using an inking process and the functional dies on the wafer are separated and sold. IC fabricators increase the yield of dies on a wafer by exploiting economies of scale. Over 1000 dies may be formed on a single wafer which measures from six to twelve inches in diameter.
Various processing steps are used to fabricate integrated circuits on a semiconductor wafer. These steps include sequential deposition of conductive and insulative layers on the silicon wafer substrate; formation of a photoresist or other mask such as titanium oxide or silicon oxide, in the form of the desired metal interconnection pattern, using standard lithographic or photolithographic techniques; subjecting the wafer substrate to a dry etching process to remove material from one or more conducting layers from the areas not covered by the mask, thereby etching the conducting layer or layers in the form of the masked pattern on the substrate; removing or stripping the mask layer from the substrate typically using reactive plasma and chlorine gas, thereby exposing the top surface of the conductive interconnect layer; and cooling and drying the wafer substrate by applying water and nitrogen gas to the wafer substrate.
The numerous processing steps outlined above are used to cumulatively apply multiple electrically conductive and insulative layers on the wafer and pattern the layers to form the circuits. Additional techniques, such as dual damascene processes, are used to form conductive vias which establish electrical contact between vertically-spaced conductive lines or layers in the circuits. The finished semiconductor product includes microelectronic devices including transistors, capacitors and resistors that form the integrated circuits on each of multiple die on a single wafer.
In the semiconductor industry, CMOS (complementary metal-oxide semiconductor) technology is extensively used in the fabrication of IC devices. CMOS technology typically involves the use of overlying layers of semiconductor material with the bottom layer being a dielectric layer and the top layer being a layer of doped silicon material that serves as a low-resistivity electrical contact gate electrode. The gate electrode, also referred to as a gate stack, typically overlies the dielectric layer.
In the semiconductor fabrication industry, silicon oxide (SiO2) is frequently used for its insulating properties as a gate oxide or dielectric. As the dimensions of device circuits on substrates become increasingly smaller, the gate dielectric thickness must decrease proportionately in field effect transistors (FETs) to approximately 3 to 3.5 n anometers. Accordingly, device performance and reliability can be adversely affected by such factors as interfacial defects, defect precursors and diffusion of dopants through gate dielectrics, as well as unintended variations in thickness in the gate oxide layer among central and peripheral regions of the layer.
As microelectronic fabrication integration levels have increased and patterned microelectronic conductor layer dimensions have decreased, it has become increasingly important within the art of microelectronic fabrication to form within microelectronic fabrications patterned microelectronic conductor layers, such as but not limited to gate electrodes within field effect transistors (FETs), as well as patterned microelectronic conductor interconnect layers, with a uniform sidewall profile. Uniform sidewall profiles are particularly desirable within gate electrodes in field effect transistors since gate electrode linewidth and profile define operational parameters of the integrated circuit within which is formed the FET. While a uniform sidewall profile is thus desirable in gate electrodes and other structures in IC devices, uniform sidewalls are, in many cases, not readily achievable.
A typical conventional process for patterning a polysilicon gate using a hard mask is shown in FIGS. 1A and 1B. A multi-layered semiconductor structure 10, shown in FIG. 1A, is initially fabricated on a substrate 12 by sequentially depositing a gate oxide layer 14, a polysilicon layer 16, a hard mask layer 18, a bottom anti-reflective coating (BARC) layer 20, and a resist layer 22 on the substrate 12. Next, the BARC layer 20 and the hard mask layer 18 are etched according to the patterned PR layer 22. This is followed by stripping of the PR layer 22 and the underlying BARC layer 20 from the patterned hard mask layer 18, to form the portion of the structure 10 which is defined by the solid lines in FIG. 1A.
Next, the polysilicon layer 16 is etched according to the patterned hard mask layer 18. This step typically involves etching of the polysilicon layer 16 using a gas mixture including chlorine, oxygen, helium and bromine. Accordingly, the polysilicon layer 16, which is etched according to the hard mask layer 18, remains on the gate oxide layer 14, as shown in FIG. 1B.
As further shown in FIG. 1B, a problem which frequently results in the etching of the polysilicon layer 16 using a chlorine-based etchant gas mixture is that a neck 17 forms in the upper end portion of the polysilicon layer 16. This necking or notched profile is undesirable since optimum semiconductor fabrication requires that the sidewalls 16a of the etched polysilicon layer 16 be as straight and uniform as possible. Accordingly, a novel method is needed for the fabrication of a polysilicon gate in such a manner that the incidence of a necking or notched configuration formed in the polysilicon gate layer is eliminated or at least substantially reduced.
An object of the present invention is to provide a novel method for fabricating a polysilicon gate.
Another object of the present invention is to provide a novel method for fabricating a polysilicon gate using a hard mask.
Still another object of the present invention is to provide a novel method for fabricating a polysilicon gate having substantially uniform sidewalls.
A still further object of the present invention is to provide a novel polysilicon gate fabrication method which eliminates or at least substantially reduces the incidence of a necking or notched profile in polysilicon gate layers.
Yet another object of the present invention is to provide a novel polysilicon gate fabrication method which includes patterning a hard mask on a polysilicon layer and etching the polysilicon layer according to the patterned hard mask using a fluorine-based etchant gas.
Another object of the present invention is to provide a novel polysilicon gate fabrication method which may include patterning a hard mask on a polysilicon layer and etching the polysilicon layer in a two-step etch process.
Still another object of the present invention is to provide a novel polysilicon gate fabrication method which may include etching of a polysilicon layer using a fluorine-based etchant gas followed by etching of the polysilicon layer using a non-fluorine-based etchant gas to eliminate or at least substantially reduce the tendency to form a necking profile in the polysilicon layer.